Frequency to digital converter, asynchronous phase sampler and digitally controlled oscillator methods

ABSTRACT

A ΔΣ frequency to digital converter includes digital feedback to an accumulator in a ring phase calculator that provides the converter output, which reduces implantation complexity. Digital gain correction is applicable to dual mode ring oscillator converters and charge pump converters, provides compensation for forward path gain error and eliminates the need to include analog gain correction in feedback. Asynchronous sampling includes correction logic to compensate for arbitrary initial conditions. A digitally-controlled oscillator (DCO) control technique causes the DCO frequency to increase or decrease by changing the state of one its frequency control elements at a time.

PRIORITY CLAIM AND REFERENCE TO RELATED APPLICATION

The application claims priority under 35 U.S.C. §119 and all applicablestatutes and treaties from prior provisional application Ser. No.62/944,797, which was filed Dec. 6, 2019, and is incorporated byreference herein.

STATEMENT OF GOVERNMENT INTEREST

This invention was made with government support under 1617545 awarded bythe National Science Foundation. The government has certain rights inthe invention.

FIELD

A field of the invention is frequency synthesis. Example applications ofthe invention are in wired and wireless communications. A particularapplication of the invention is in wireless transceivers for thegeneration of radio frequency (RF) local oscillator signals used toup-convert and down-convert transmitted and received RF signals.

BACKGROUND

Evolving wireless communication standards place increasingly stringentperformance requirements on the frequency synthesizers that generate RFlocal oscillator signals for up and down conversion in wirelesstransceivers. Conventional analog fractional-N PLLs with digitaldelta-sigma (ΔΣ) modulation are the current standard for such frequencysynthesizers because of their excellent noise and spurious toneperformance. See, e.g., T. A. Riley, M. A. Copeland, T. A. Kwasniewski,“Delta-sigma modulation in fractional-N frequency synthesis,” IEEEJournal of Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May 1993.Unfortunately, they require high-performance analog charge pumps andlarge-area analog filters, so the trends of CMOS technology scaling andincreasingly dense system-on-chip integration have created aninhospitable environment for them.

Digital fractional-N PLLs have been developed over the last decade toaddress this problem. See, e.g., C. Hsu, M. Z. Straayer, M. H. Perrott,“A Low-Noise, Wide-BW 3.6 GHz Digital ΔΣ Fractional-N FrequencySynthesizer with a Noise-Shaping Time-to-Digital Converter andQuantization Noise Cancellation,” IEEE International Solid-StateCircuits Conference, pp. 340-341, February 2008. They avoid large analogloop filters and can tolerate device leakage and low supply voltageswhich makes them better-suited to highly-scaled CMOS technology thananalog PLLs. They are increasingly used in place of analog PLLs asfrequency synthesizers, but they have yet to fully replace analog PLLsin high-performance wireless applications. While both analog and digitalfractional-N PLLs introduce quantization noise, in prior digital PLLsthe quantization noise has higher power or higher spurious tones than incomparable analog PLLs. Consequently, they exhibit worse phase noise orspurious tone performance than the best analog PLLs. See, e.g., K. Wang,A. Swaminathan, I Galton, “Spurious-Tone Suppression Techniques Appliedto a Wide-Bandwidth 2.4 GHz Fractional-N PLL,” IEEE Journal ofSolid-State Circuits, vol. 43, no. 12, pp. 2787-2797, December 2008.Digital PLLs based on second-order ΔΣ frequency-to-digital conversion(FDC-PLLs) offer a potential solution to this problem in that theirquantization noise ideally is equivalent to that of an analog PLL withsecond-order ΔΣ modulation. To the knowledge of the inventors, priorsecond-order FDC-PLLs incorporate charge pumps and ADCs. See, e.g., W.T. Bax, M. A. Copeland, “A GMSK Modulator Using a ΔΣ FrequencyDiscriminator-Based Synthesizer,” IEEE Journal of Solid-State Circuits,vol. 36, no. 8, pp. 1218-1227, August 2001; C. Venerus, I. Galton,“Delta-Sigma FDC Based Fractional-N PLLs,” IEEE Transactions on Circuitsand Systems I: Regular Papers, vol. 60, no. 5, pp. 1274-1285, May 2013.

The state-of-the art has been previously advanced by the followingFDC-PLL architectures. See, C. Weltin-Wu, G. Zhao, and I. Galton, “AHighly-Digital Frequency Synthesizer Using Ring-OscillatorFrequency-to-Digital Conversion and Noise Cancellation,” IEEE Int.Solid-State Circuits Conf (ISSCC) Dig. Tech. Papers, February 2015, pp.1-3; C. Weltin-Wu, G. Zhao, and I. Galton, “A 3.5 GHz DigitalFractional-N PLL Frequency Synthesizer Based on Ring OscillatorFrequency-to-Digital Conversion,” IEEE J. Solid-State Circuits, vol. 50,no. 12, pp. 2988-3002, December 2015; C. Weltin-Wu, E. Familier, and I.Galton, “A Linearized Model for the Design of Fractional-N Digital PLLsBased on Dual-Mode Ring Oscillator FDCs,” IEEE Trans. Circuits Syst. I,Reg. Papers, vol. 62, no. 8, pp. 2013-2023, August 2015.

A high-level block diagram of a second-order ΔΣ FDC-based fractional-NPLL 100 consistent with the state-of-the-art in the previous paragraphis shown in FIG. 1. It consists of a ΔΣ FDC 102, a digital loopcontroller (DLC) 104 with quantization noise cancellation (QNC) viaadder 107, a digital loop filter 108 and a digitally-controlledoscillator (DCO) 110. The signal v_(ref)(t) is the output of a referenceoscillator with frequency f_(ref) and v_(PLL)(t) is the PLL outputwaveform. Ideally, v_(PLL)(t) is periodic with frequencyf_(PLL)=(N+a)f_(ref), where N is a positive integer and a has afractional value that can range from −½ to ½. Specifically,

$\begin{matrix}{\mspace{79mu} {{{y\lbrack n\rbrack} = {{- \alpha} - {e_{PLL}\lbrack m\rbrack} + \text{?}}}{\text{?}\text{indicates text missing or illegible when filed}}}} & (1)\end{matrix}$

where e_(q)[n] is the quantization error introduced by the ΔΣ FDC ande_(PLL)[n] is a measure of the average frequency error of v_(PLL)(t)over the nth reference period. The ê_(q)[n] sequence is an estimate ofe_(q)[n]. It is added via the second adder after passing through the1−z⁻¹ differentiator. It is used to partially cancel the contribution ofe_(q)[n] at the input of the digital loop filter (DLF) within the DLC.By cancelling the quantization error prior to the loop filter, QNCallows the PLL's bandwidth to be increased without significantlydegrading the PLL's phase noise.

A simplified block diagram of the ΔΣ FDC from C. Weltin-Wu, E. Familier,and I. Galton, “A Linearized Model for the Design of Fractional-NDigital PLLs Based on Dual-Mode Ring Oscillator FDCs,” IEEE Trans.Circuits Syst. I. Reg. Papers, vol. 62, no. 8, pp. 2013-2023, August2015 is shown in FIG. 2A. It consists of a PFD (Phase FrequencyDetector) with top output u(t), a multi-modulus divider with outputv_(div)(t), a DMRO (Dual-Mode Ring Oscillator), a digital ring phasecalculator (RPC), and a 2−z⁻¹ digital feedback block with output v[n]that controls the divider. Although not shown in FIG. 2A for simplicity,the RPC's accumulator clips to keep its output in the range −2≤r[n]<3.This reduces the PLL's worst-case locking time but has no effect on thePLL's locked behavior. The PFD and divider are identical to those inanalog PLLs.

Each reference period, the signal encoded in the width of the u(t) pulseis accumulated by the DMRO. Then, the outputs of the DMRO, whichrepresent a quantized version of its phase, are sampled and processed bythe RPC to generate y[n] and −ê_(q)[n].

The DMRO is implemented as a ring of NR nominally identical delay cells.Ideally, its instantaneous frequency is f_(high) when u(t) is high andf_(low) when u(t) is low, where

$\begin{matrix}{{{A\frac{\left( {f_{high} - f_{low}} \right)}{f_{PLL}}} = 1},} & (2)\end{matrix}$

and A is a design parameter.

Each reference period, the quantized DMRO phase, p_(R)[n], is computedfrom the sampled DMRO output lines. As indicated in FIG. 2A, p_(R)[n] ispassed through a 1−z⁻¹ block, and a positive constant, M, is subtractedfrom the result prior to the multiplication by A and accumulation. Theseoperations yield r[n], which is a fixed-point measure of −a −e_(pLL)[n]in units of cycles per reference period. The three most significant bits(MSBs) of r[n] correspond to the integer part of r[n], whereas theremaining least significant bits (LSBs) correspond to the fractionalpart of r[n].

The operation of the divider is such that adjacent rising edges ofv_(div)(t) are separated by N v[n] PLL output periods. Ideally, v[n]would be set to 2r[n]−r[n−1], but dividers can only count integernumbers of PLL output periods and r[n] contains both integer andfractional parts. Therefore, it is necessary to instead use just theinteger part of r[n], i.e., y[n], so that v[n] =2y[n]−y[n−1] isinteger-valued. Given that y[n] is a quantized version of r[n], thefractional part of r[n], i.e., −ê_(q)[n], is the negative of thecorresponding quantization error. The DLC uses −ê_(q)[n] to perform QNC.

The behavior of the system shown in FIG. 2A is identical to that of thesecond-order ΔΣ modulator shown in FIG. 3A. The phase quantizationoperation performed by the DMRO is denoted by Q, and modeled as a finequantizer of step-size Δ_(r)=(2N_(R))⁻¹. Its quantization error,e_(qr)[n], corresponds to the residual quantization error that is leftafter QNC. The quantization operation that occurs at the output of theRPC is denoted as Q_(c) and modeled as a coarse quantizer with step-sizeΔ_(c)=1. If 2N_(R)/A is integer-valued, then the blocks contained in thedashed contour in FIG. 3A are equivalent to an accumulator followed by aquantizer, Q, with unity step-size and associated error given by

e _(q)[n]=Ae _(qr)[n]+{circumflex over (e)}_(q)[n].   (3)

In this case, y[n] is given by (1) and the system's self-ditheringproperty causes e_(q)[n] to have a power spectral density (PSD)equivalent to that of a zero-mean white noise sequence with variance1/12.

This ΔΣ FDC suffers from two issues. One issue is tight timingconstraints on both the digital part of the ΔΣ FDC and the divider. Theother issue is high sensitivity to non-ideal DMRO frequencies for higherPLL bandwidths. Once the ΔΣ FDC locks, the rising edges of v_(div)(t)succeed and precede rising and falling edges of v_(ref)(t), respectivelyTherefore, as implied by FIG. 2A, after the nth rising edge ofv_(div)(t), the ΔΣ FDC must compute y[n] and use it along with y[n−1] toform v[n], which the divider then uses to determine the (n+1)th risingedge of v_(div)(t). This limits the time available for the ΔΣ FDC toprocess the u(t) pulse and compute y[n] to approximately one referenceperiod and requires a divider that is capable of loading the dividermodulus in the middle or toward the end of the divider count. Thesefeatures tend to increase the power consumption, circuit area, andcomplexity of the divider.

ΔΣ FDC-based PLLs are not highly sensitive to non-ideal values off_(high) and f_(low), i.e., values of f_(high) and f_(low) that do notexactly satisfy (2), in much the same way that a second-order ΔΣmodulator is not sensitive to deviations in the gain of its secondaccumulator. Nevertheless, the need to adjust the DMRO each time fatchanges so that f_(high) and f_(low) at least approximately satisfy (2)complicates the DMRO design. Moreover, the accuracy with which (2) mustbe satisfied increases significantly with PLL bandwidth to the pointthat process, voltage, and temperature variations cause f_(high) andf_(low) to deviate from their ideal values enough to significantlydegrade the PLL's phase noise.

TABLE OF ABBREVIATIONS

The following list of abbreviations are used throughout thisapplication:

ADC Analog to Digital Converter

CMOS Complementary Metal Oxide Semiconductor

CP Charge Pump

DC Direct Current

DCO Digitally Controlled Oscillator

DMRO Dual-Mode Ring Oscillator

ΔΣ Delta-Sigma

DLC Digital Loop Controller

DLF Digital Loop Filter

FCE Frequency Control Element

FDC Frequency to Digital Converter

FSM Finite State Machine

IFS Incremental Frequency Switching

IS-FSM Incremental-Switching Finite State Machine

ISL Incremental Switching Logic

LFCE Latched-Frequency Control Element

LUT Look-Up Table

MSB Most Significant Bit

PEDC Phase Error to Digital Converter

PFD Phase Frequency Detector

PLL Phase-Locked Loop

PSD Power Spectral Density

RF Radio Frequency

RO Ring Oscillator

RPC Ring Phase Calculator

QNC Quantization Noise Cancellation

SUMMARY OF THE INVENTION

A preferred embodiment is a delta-sigma frequency-to-digital converter.The converter includes a phase-frequency detector that receives aperiodic reference signal. A dual-mode ring oscillator is driven by anoutput of the phase-frequency detector. A ring phase calculator samplesoutputs of the dual-mode ring oscillator to calculate phase of thedual-mode ring oscillator. Digital feedback is provided to anaccumulator in the ring phase calculator that provides the converteroutput. Feedback of a delayed version of the converter output isprovided through a divider to the phase-frequency detector.

The preferred converter or other converters can benefit from a preferreddigital background correction method. A preferred technique can beimplemented in the ring phase calculator. Preferably, the digitalbackground calibration comprises a signed least-mean square (LMS)-likeloop with gain K and output g_(n), which digitally compensates forforward path gain error caused by δ≠1 (forward gain in the absence ofgain correction).

Another converter that can benefit from the digital backgroundcalibration is a charge pump-based converter. The converter includes aphase-frequency detector that receives a periodic reference signal. Acharge pump that charges and discharges a capacitor. A one-shot circuitthat prevents the magnitude of the charge pump output to grow withoutbound. An analog-to-digital converter is driven by an output of thecharge pump. A multi-modulus divider provides feedback to thephase-frequency detector. Digital background calibration is provided bya multiplier at the output of the analog-to-digital converter to correctfor deviations of charge pump currents and capacitance of capacitor fromtheir ideal values.

Asynchronous phase sampling can also be implemented. A preferred ringoscillator delay-free asynchronous phase sampler samples outputs of thering oscillator (RO). A cycle counter with two counters is clocked bythe rising and falling edges, respectively, of the output of the RO. Aphase decoder processes the outputs of the RO and selects a sampledcounter output that was not changing when the sampling event occurred.Correction logic to compensate for arbitrary initial conditions of theRO and counters within the cycle counter.

A digitally-controlled oscillator (DCO) control technique of theinvention is applicable to FDC-based PLLs discussed above but is widelyapplicable to other digital PLLs. The DCO control technique causes theDCO frequency to increase or decrease by changing the state of one itsfrequency control elements (FCEs) at a time includes a bank of FCEs tocontrol the DCO frequency, the FCE bank having an array of latched-FCEs(LFCEs). A digital interface accepts an input codeword and outputs twocontrol signals and their inverted versions to control the FCEs' bank.The array of LFCEs is connected to the control signals through anintra-network of switches, with each top switch being controlled by thestate of the LFCE to its right (or an inverted version of it) and eachbottom switch being controlled by the state of the LFCE to its left (oran inverted version of it). A DCO digital interface includes anincremental switching logic (ISL) and an incremental-switchingfinite-state-machine (IS -FSM). the ISL splits the input codeword intoits integer and fractional parts, digitally re-quantizing the fractionalpart and adding it to the integer part of the input codeword, an outputof this operation being passed through control logic including aclipper, an accumulator, a carry-generator and an adder, wherein thecontrol logic outputs changes in its input (limited to ±1) and the carryis added to the next sample, to serialize a change in the control logicinput. An output of the ISL is a signal that takes on values from {−1,0, 1} and is passed to the IS-FSM, wherein the IS-FSM generates twocontrol signals and their inverted versions that control the array ofLFCEs.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be explained in greater detail hereinafter on thebasis of exemplary embodiments illustrated in the drawings, in which:

FIG. 1 (Prior Art) is a high-level block diagram of a second-order ΔΣFDC-based digital fractional-N PLL with quantization noise cancellation(QNC);

FIG. 2A (Prior Art) simplified block diagram of the DMRO-based ΔΣ FDCdescribed in C. Weltin-Wu, E. Familier, and I. Galton, “A LinearizedModel for the Design of Fractional-N Digital PLLs Based on Dual-ModeRing Oscillator FDCs,” IEEE Trans. Circuits Syst. I. Reg. Papers, vol.62, no. 8, pp. 2013-2023, August 2015;

FIG. 2B is a simplified block diagram of the DMRO-based ΔΣ FDC accordingto the present invention;

FIG. 3A (Prior Art) is a single processing equivalent of the FIG. 2ADMRO-based ΔΣ FDC;

FIG. 3B is a single processing equivalent of the FIG. 2B DMRO-based ΔΣFDC;

FIG. 4A (Prior Art) shows example timing diagrams for the FIG. 2A ΔΣ FDC

FIG. 4B shows example timing diagrams for the present ΔΣ FDC of FIG. 2B;

FIG. 5A is a behavioral model of the present ΔΣ FDC of FIG. 2B;

FIG. 5B is a behavioral model of the FIG. 1 PLL with the present ΔΣ FDCof FIG. 2B;

FIG. 6 shows a portion of the ring phase calculator of present ΔΣ FDC of

FIG. 2B with application of a preferred digital gain correction method;

FIG. 7 is the behavioral model of FIG. 5A with the addition of the FIG.6 digital gain correction method;

FIG. 8A (Prior Art) shows a charge pump based ΔΣ FDC;

FIG. 8B shows a preferred digital gain correction method applied to the

FIG. 8A charge pump based ΔΣ FDC;

FIG. 9 shows a preferred delay-free asynchronous phase sampling for theFIG. 2B DMRO or any system where the phase of a ring oscillator (RO)needs to be sampled with a clock signal asynchronous to the RO'sfrequency;

FIGS. 10A and 10B (Prior Art) show a PLL and a conventional controllerfor its DCO;

FIG. 11 (Prior Art) shows a conventional PLL controller;

FIG. 12 shows a preferred incremental frequency-switching controller forthe DCO in the FIGS. 10A or FIG. 1 PLL;

FIG. 13 is an example that describes operation of the incrementalfrequency-switching controller of FIG. 12;

FIG. 14A shows a bank topology implementation of the DCO of FIG. 10A;FIG. 14B shows details of the latched-FCEs;

FIG. 15A shows details of a preferred incremental frequency-switchingcontroller implementation for the FIG. 12 incrementalfrequency-switching controller and FIG. 15B a state diagram foroperation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments provide a ΔΣ FDCs that reduce implementationcomplexity and improve performance. The invention also provides a methodfor digital gain correction. A preferred digital background calibrationmethod compensates for forward path gain error and eliminates the needto include analog gain correction in feedback.

A preferred ΔΣ FDC architecture has relaxed timing constraints and a 3×smaller phase-frequency detector (PFD) output pulse-width span comparedto prior state-of-the art architectures discussed in the background. Thepreferred architecture is therefore simpler to implement and is amenableto higher-frequency reference signals for any given PLL outputfrequency, which is useful because increasing the reference frequencyreduces the contributions of the reference signal phase noise, ΔΣ FDCquantization error, and DMRO phase noise to the PLL's output phasenoise.

The DMRO in a DMRO-based ΔΣ FDC is designed to oscillate at one of twofrequencies at any given time. These frequencies, denoted as f_(high)and f_(low), ideally have a specific relationship to the PLL outputfrequency, f_(PLL). In prior art DMRO-based ΔΣ FDCs, f_(high) andf_(low) are adjusted each time f_(PLL) is changed to approximate thisideal relationship, which adds complexity to the DMRO design.Furthermore, while the PLL's performance is relatively insensitive todeviations of f_(high) and f_(low) from their ideal values forlow-to-moderate PLL bandwidths, this is not the case for high PLLbandwidths.

The invention includes a digital background calibration that addressesthese issues. Rather than dynamically adjusting f_(high) and f_(low) bycontrolling the DMRO's analog circuitry as a function offpn, itdynamically adjusts digital circuitry to compensate for error that wouldotherwise be caused by non-ideal values of f_(high) andfiow. Moreover,it does so with much finer resolution than prior art ΔΣ FDCs are able toadjust the DMRO to tune f_(high) and f_(low). These benefits greatlysimplify the DMRO, which can now be designed to have fixed values off_(high) and f_(low), and significantly reduce phase noise for high PLLbandwidths.

Preferred embodiments of the invention will now be discussed withrespect to the drawings. The drawings may include schematicrepresentations, which will be understood by artisans in view of thegeneral knowledge in the art and the description that follows.

A preferred embodiment ΔΣ FDC 200 is shown in FIG. 2B. The sequencesv[n], p_(R)[n] and d_(R)[n] and the signals u(t) and v_(div)(t) in FIG.2B different from those in FIG. 2A but are labelled the same because thesignal sequences play the same role in each. The input, v_(ref)(t), tothe ΔΣ FDC 200 is a periodic reference signal and is provided to aphase-frequency detector PFD 202. With each reference period, thequantized DMRO phase, p_(R)[n], from a DMRO 204 is received by a ringphase calculator RPC 205 and is computed by its cycle counter and phasedecoder 206 from the sampled DMRO output lines. As indicated in FIG. 2B,p_(R)[n] representing the sampled and quantized DMRO phase is passedthrough a 1−z⁻¹ differentiator 208, and a positive constant M, whichrepresents the average number of cycles that the DMRO advances perreference period, is subtracted by M-adder 210 from the result prior tothe multiplication 212 by A (design parameter chosen to nominally settotal forward gain equal to 1) and accumulation by accumulator 214.Instead of feeding back the multi-modulus divider control sequence2y[n]−y[n−1] through a divider 216 as in FIG. 2A, 2y[n−1] is fed backdirectly to the input of the accumulator 214 within the RPC 205 by aadder 218, and only a delayed version of the FDC output y[n−1] is fedback through the divider 216. The direct feedback to the accumulator 214simplifies the architecture and improves performance.

The ΔΣ FDC 200 is equivalent to the functional representation in FIG.3B. That function is also identical to the function in FIG. 3A under thecondition that 2N_(R)/A is integer-valued.

In the FIG. 2A and 3A prior ΔΣ FDC, once it locks, the DMRO locks to anaverage frequency of Mf_(ref), which minimizes the potential forfractional spurs if M is integer-valued. Specifically, given that r[n]is bounded when the ΔΣ FDC is locked, the input to the accumulatorwithin the RPC, and, hence, the M-adder output, must be zero-mean, whichcan only happen if the DMRO phase advances, on average, M cycles perreference period.

In the ΔΣ FDC 200, the average of the M-adder 210 output is forced tozero by subtracting a constant 2 a from the input of the accumulator214, which forces average DMRO frequency to be given by Mf_(ref)Reasoning and (1) imply that without the 2 a subtraction at adder 218,the local feedback around the accumulator 214 would cause the output ofthe M-adder to have an average of 2A⁻¹a. In this case, the DMRO wouldlock to (M−24 ⁻¹a)f_(ref), which would increase the potential forfractional spurs.

The 2 a subtraction slightly increases the PLL's digital complexityrelative to a comparable PLL based on FIG. 2A. For instance, in the PLLimplementation simulated, the cycle counter and phase decoder's output,p_(R)[n], has 10 fractional bits, a has 20 fractional bits, and A=1, sothe 2 a subtraction nearly doubles the number of fractional bitsrequired to represent the RPC accumulator's input. Nonetheless, thenumber of fractional bits in the DLF input is determined by a regardlessof which ΔΣ FDC is used, so the 2 a subtraction in the ΔΣ FDC 200 onlyaffects the RPC's accumulator 214. Hence, it represents only a minorincrease in the PLLs overall digital complexity. Moreover, this increasein complexity can be offset by additional features described below. Whenthe ΔΣ FDC 200 is used in a PLL, an output span of the phase-frequencydetector 202 can advantageously be smaller than twice the period of PLLoutput.

It follows from FIG. 3B that for the ΔΣ FDC 200 the discrete-timetransfer function from the input to the second accumulator output has apole at DC, which suggests that the system is unstable. Although the 2 aterm injected within the RPC 205 causes the DC component at the outputof the second accumulator to be zero, noise present at this node cancause the magnitude of the accumulator output to grow without bound.However, the second accumulation shown in FIG. 3B is performed by theDMRO 204, so this is not an issue in practice because the DMRO 204behaves as an accumulator with infinite output range. Specifically,provided the cycle counter 206 within the RPC 205 does not roll-overmore than once per reference period, which can be ensured by design,then the 1−z⁻¹ differentiator 208 within the RPC 205 can unwrap thesampled DMRO phase and retrieve the information encoded in it, therebyallowing the magnitude of the second accumulator's output in FIG. 3B tobe arbitrarily large.

Features to offset additional complexity include relaxed timingconstraints. FIG. 4A shows example timing diagrams for the FIG. 2A ΔΣFDCs and FIG. 4B for the present ΔΣ FDC 200 of FIG. 2B, where the timesequences t_(n) and τ_(n), for n=0, 1, 2, . . . , are the times of thenth rising edges of v_(ref)(t) and v_(div)(t), respectively, and the nthdivider modulus is the number of PLL output periods between τ_(n−1) andτ_(n). In this example, the DMRO phase is sampled at timesγn=t_(n−1)+T_(ref)/2, where T_(ref)=1/f_(ref) is the reference period,and the nth divider modulus can be loaded at time t_(n) at the latest.

In the FIG. 2A ΔΣ FDC, the nth divider modulus is given byN−(2y[n−1]−y[n−2]), but as illustrated in FIG. 4A, y[n−1] cannot becomputed before the DMRO phase is sampled at γ_(n)>τ_(n−1). It followsthat the nth divider modulus can only be loaded once y[n−1] is readyaround the middle or near the end of the count, which increases thedivider's complexity. Furthermore, as the divider modulus must beupdated before t_(n), the amount of time available for the ΔΣ FDC tocompute y[n−1] is limited to T_(ref)/2.

As illustrated in FIG. 4B, the present ΔΣ FDC 200 has much more relaxedtiming constraints. In this case, the nth divider modulus is given byN−y[n−2]. By the time of the (n−1)th rising edge of v_(div)(t), the ΔΣFDC 200 has already had a duration of more than T_(ref)/2 to computey[n−2], so the next count can start with a known divider modulus.Alternatively, the computation of y[n−2] can take up to T_(ref), and thedivider modulus can be updated near the beginning of the current count.In either case, compared to the FIG. 2A ΔΣ FDC, the present ΔΣ FDCallows for simpler divider topologies to be used and imposes looserdigital timing constraints on the ΔΣ FDC.

Another feature is reduced PFD output span. For the FIG. 2A ΔΣ FDC,e_(PLL)[n] in (1) is given by

e _(PLL)[n]=Ψ_(PLL)[n]−(N+a)Ψ_(ref)[n]−A(Ψ_(DMRO)[n]−Ψ_(DMRO)[n−1]),  (4)

the e_(q)[n] sequence is bounded by

−1<e _(q)[n]≤0,   (5)

and the width of u(t) is given by

τ_(n) −t _(n) =T _(ū)+(−y[n−1](N+a)Ψ_(ref)[n]−AΨ _(DMRO)[n−1]−e_(q)[n−1]+e _(q)[n−2]−a) T _(PLL),   (6)

where Ψ_(PLL)[n], Ψ_(ref)[n] and Ψ_(DMRO)[n] are the phase noise changesper reference period of v_(PLL)(t), v_(ref)(t) and the DMRO,respectively, and

$\begin{matrix}{T_{\overset{¯}{u}} = \frac{M - {T_{ref}f_{low}}}{f_{high} - f_{low}}} & (7)\end{matrix}$

is the average width of the u(t) pulse.

Suppose b_(PLL) and b_(DMRO) are the maximum magnitudes of e_(PLL)[n]and Ψ_(DMRO)[n], respectively, so

|e _(PLL)[n]|<b _(PLL) and |Ψ_(DMRO)[n]|<b_(DMRO)   (8)

for all n. Then, it follows from (1), (4)-(6) and (8) that the maximumspan of u(t), ΔT_(u), which is defined as

$\begin{matrix}{{{\Delta T_{u}} = {2{\max\limits_{n}{{\tau_{n} - t_{n} - T_{\overset{¯}{u}}}}}}},} & (9)\end{matrix}$

satisfies

ΔT _(u)<2 (3+2b _(PLL) +Ab _(DMRO))T _(PLL).   (10)

Analysis of the present ΔΣ FDC 200 yields (4), (5), and the followingexpression for the width of the u(t) pulse during the nth referenceperiod:

τ_(n) −t _(n) =T _(ū)(y[n−1]−Ψ_(PLL)[n]+(N+a) Ψ_(ref)[n]−AΨ_(DMRO)[n−1]e _(q)[n−1]+e _(q)[n−2]+a) T _(PLL).   (11)

where T_(ū) is also given by (7). Hence, (1), (4), (5), (8), (9) and(11) imply that, for the present ΔΣ FDC 200, ΔT_(u) satisfies

ΔT _(u)<2 (1+2b _(PLL) +Ab _(DMRO)) T _(PLL).   (12)

In practice, b_(PLL), b_(DMRO)<<1, so (10) and (12) imply that ΔT_(u)for the present ΔΣ FDC 200 is approximately a third of that of the priorFIG. 2A ΔΣ FDC.

A smaller ΔT_(u) allows for a larger minimum difference between thephases of v_(ref)(t) and v_(div)(t), so it is beneficial as it mitigatesspurs generated as a consequence of variations in supply voltage of thePFD 202 when v_(ref)(t) and v_(div)(t) are close in phase. Additionally,reducing ΔT_(u) mitigates spurs from non-ideal DMRO behavior byincreasing the time available for the DMRO 204's instantaneous frequencyerror transients to die out each reference period.

Another feature is the ability to handle higher-frequency referencesignals. The relaxed timing constraints and smaller ΔT_(u) of thepresent ΔΣ FDC 200 allows for the use of higher-frequency referencesignals, which lowers the contribution to the PLL's phase noise from allnoise sources within the ΔΣ FDC. As in conventional fractional-N PLLs,the contribution of the reference signal to the PLL output phase noisePSD, S_(PLL)(f), is proportional to (N+a)². Equations (1), (4) and FIG.1 imply that the ΔΣ FDC quantization error and the DMRO phase noiseappear first-order shaped at the DLF input (p[n] in FIG. 1), so theircontribution to S_(PLL)(f) is proportional to sin²(πT_(ref)f).Additionally, the PSD of the quantization error is proportional toT_(ref). Therefore, increasing f_(ref) by a factor of x for a givenf_(PLL) with all other things being the same reduces the contributionsto the PLL's phase noise from the reference signal, ΔΣ FDC quantizationerror, and DMRO by 20 log(x), 30 log(x) and 20 log(x), respectively.

Digital Gain Calibration Method (FIG. 6).

As explained above, the behavior of the present ΔΣ FDC is identical tothat of a second-order ΔΣ modulator provided (2) holds and 2N_(R)/A isinteger-valued. However, in practice

$\begin{matrix}{{{A\frac{f_{high} - f_{low}}{f_{PLL}}} = \delta^{- 1}},} & (13)\end{matrix}$

where the deviation of the factor δ from its ideal value of 1 is the ΔΣFDC's forward path gain error. This error degrades the system'sself-dithering property and, as shown below, it reduces the extent towhich QNC cancels the error introduced by the ΔΣ FDC's coarsequantization operation.

Analysis presented in [C. Weltin-Wu, E. Familier, and I. Galton, “ALinearized Model for the Design of Fractional-N Digital PLLs Based onDual-Mode Ring Oscillator FDCs,” IEEE Trans. Circuits Syst. I. Reg.Papers, vol. 62, no. 8, pp. 2013-2023, August 2015] can be modified with(13) instead of (2) for the present ΔΣ FDC, 200 which yields thebehavioral model of the ΔΣ FDC shown in FIG. 5A. The model is similar tothat shown in FIG. 3B, except that e_(PLL)[n] is given by (4) with δAinstead of A, and the gain of the second accumulator is (6A)⁻¹ insteadof A⁻¹. An analysis also be performed to obtain a linearized model ofthe ΔΣ FDC PLL shown in FIG. 1 with the present ΔΣ FDC 200 and (13)instead of (2). The resulting model is shown in FIG. 5B, whereθ_(ref)(t), θ_(DMRO)(t), θ_(DCO)(t) and θ_(PLL)(t) are the phase errorwaveforms of the reference signal, DMRO, DCO and PLL output,respectively, L(z) is the DLF's transfer function, K_(DCO) is the DCOgain (i.e., the amount in Hz by which the DCO frequency changes when theDCO input changes by unity) and

H(z)=1−(1−δ⁻¹)z ⁻².   (14)

It follows from FIG. 5B that the discrete-time transfer functions frome_(qr)[n] and e_(q)[n] to the input of the DLF, p[n], are given by

$\begin{matrix}{{A\frac{\left( {1 - z^{- 1}} \right)}{H(z)}\frac{1}{1 + {T(z)}}\mspace{14mu} {and}\mspace{14mu} \left( {1 - \delta^{- 1}} \right)z^{- 2}\frac{\left( {1 - z^{- 1}} \right)}{H(z)}\frac{1}{1 + {T(z)}}},} & (15)\end{matrix}$

respectively, where

$\begin{matrix}{{T(z)} = {\delta^{- 1}K_{DCO}T_{ref}\frac{z^{- 2}{L(z)}}{\left( {1 - z^{- 1}} \right){H(z)}}}} & (16)\end{matrix}$

is the discrete-time loop gain of the PLL. The right-most expression in(15) implies that if δ=1, then p[n] does not depend on ê_(q)[n], but ifδ≠1, then e_(q)[n] leaks into the DLF input. As the power of e_(q)[n] ismuch larger than that of e_(qr)[n] in practice, this can be problematic,particularly for high PLL bandwidths. For instance, in the DMRO-basedPLL presented in C. Weltin-Wu, G. Zhao, and I. Galton, “A 3.5 GHzDigital Fractional-NPLL Frequency Synthesizer Based on Ring OscillatorFrequency-to-Digital Conversion,” IEEE I Solid-State Circuits, vol. 50,no. 12, pp. 2988-3002, December 2015, A=1 and N_(R)=13, so Δ_(r)=1/26and the power of e_(q)[n] is approximately 28 dB larger than that ofe_(qr)[n] (recall that Δ_(c)=1). In this case, (15) with A=1 impliesthat a ΔΣ FDC forward path gain error corresponding to δ⁻¹=1±0.08 wouldintroduce an additional error component that depends on ê_(q)[n] withapproximately double the power of the component that depends one_(qr)[n]. This would significantly increase the PLL output phase noisePSD at offset frequencies where the ΔΣ FDC quantization errorcontribution dominates those of the other noise sources.

A digital gain calibration method of the invention can address theseissues. The present digital gain calibration method modifies the ΔΣFDC's RPC 206, the details of which are shown in FIG. 6, where sgn(x) =1if x≥0 and 1 otherwise. To minimize clutter, FIG. 6 only shows a portionof the RPC 206.

The gain calibration technique consists of a signed least-mean square(LMS)-like loop with gain K and output g^(n), which digitallycompensates for forward path gain error caused by δ≠1. It is based onthe following two results. The first result is that d_(R)[n] in FIG. 2Bcan be multiplied in a multiplier 602 by a constant factor gt, tocompensate for non-ideal DMRO frequencies. In the presence of thisfactor, the transfer function from ê_(q)[n] to p[n] is given by

$\begin{matrix}{{\left( {1 - {g_{n}\delta^{- 1}}} \right)z^{- 2}\frac{\left( {1 - z^{- 1}} \right)}{H_{g}(z)}\frac{1}{1 + {T_{g}(z)}}},} & (17)\end{matrix}$

where H_(g)(z) is given by (14) with δ⁻¹ replaced by g_(n)δ⁻¹ andT_(g)(z) is given by (16) with H_(g)(z) and g_(n)δ⁻¹ instead of H(z) andδ⁻¹, respectively. It follows from (17) that g_(n)=δ makes thecontribution to p[n] from ê_(q)[n] equal to zero. The second result isthat g_(n)(d_(R)[n]−d_(R)[n−1]) equals −v[n−1]−a plus zero-mean errorwhen gt, is equal to its ideal value of δ, i.e.,δ(d_(R)[n]−d_(R)[n−1])=−v[n−1]−a plus zero-mean error.

These observations suggest that, provided it is stable, the gaincalibration feedback loop ramps gt, up or down until it reaches thepoint where the input to the accumulator with gain K is zero-mean noise.FIG. 6 implies that this happens wheng_(n)(d_(R)[n]−d_(R)[n−1])+v[n−1]+a is uncorrelated with v[n−1]+a.Therefore, to the extent that the error component inδ(d_(R)[n]−d_(R)[n−1]) is uncorrelated with v[n−1]+a, the systemconverges to the ideal value of g_(n)=δ.

In addition to preventing ê_(q)[n] from leaking into the PLL loop, theproposed calibration technique also allows for the use of DMROtopologies with coarse frequency tuning or no tuning at all. This notonly simplifies the design and implementation of the DMRO, but alsosimplifies the system as it renders feedback loops that tune f_(high)and f_(low) as a function of f_(PLL) unnecessary.

The present calibration technique somewhat increases the digitalcomplexity of the ΔΣ FDC 200, but typically does not add significantlyto the PLL's overall power or area consumption. For example, in the PLLimplementation described below, both d_(R)[n] and g_(n) have 10fractional bits, so 20 fractional bits are required to representg^(n)d_(R)[n]. Given that a also has 20 fractional bits, the gaincalibration technique negligibly increases the number of fractional bitsrequired to represent the RPC accumulator's input. Therefore, as thecalibration technique's digital LMS loop is relatively simple, thef_(ref)-rate digital multiplier prior to the RPC's accumulatorrepresents most of the calibration technique's added complexity.

A convergences analysis shows the digital calibration causes g_(n) toconverge to its ideal value. FIG. 7 shows the block diagram of FIG. 5Amodified to include the gain calibration technique of FIG. 6, whereε_(n) is the error in g_(n) at sample time n, which is defined as

ε_(n)=δ⁻¹ g _(n)−1.   (18)

For any fixed value of gn and neglecting e_(qr)[n], FIG. 7 implies thata[n] is equal to (1+ε_(n))e[n], because the two 1−z⁻¹ blocks cancel thetwo accumulators in the path between e[n] and a[n]. The gain calibrationloop adds v[n−1]+a, which is an estimate of e[n], to a[n], andmultiplies the result by the sign of v[n−1]+a to obtain a measure ofε_(n), b[n], which is approximately equal to −ε_(n)|e[n]1.

More precisely, FIGS. 7 and (18) imply that e[n] is given by

e[n]=−v[n−1]−a−e_(PLL)[n],   (19)

and that a[n] can be written as

$\begin{matrix}{{{a\lbrack n\rbrack} = {{\left( {1 + ɛ_{n}} \right){e\lbrack n\rbrack}} + {\left( {ɛ_{n} - ɛ_{n - 1}} \right){\sum\limits_{i = 0}^{n - 1}{e\lbrack i\rbrack}}} + {a_{e}\lbrack n\rbrack}}},} & (20)\end{matrix}$

where a_(e)[n] is the contribution of e_(qr)[n] to a[n]. Substituting(19) into (20) adding v[n−1]+a to the result, and then multiplying theresulting expression by sgn(v[n−1]+a) yields

b[n]=ε_(n)|v[n−1]+a|+b_(e)[n],   (21)

where b_(e)[n] is error that arises from the error in the estimate ofe[n], the contribution of e_(qr)[n], and g_(n) not being constant.

FIG. 7 together with (18) and (21) further imply that

ε_(n+1)=(1−δ⁻¹ K|v[n−1]+a|)ε_(n)+δ⁻¹ Kb _(e)[n],   (22)

from which it follows that

ε _(n+1)=(1−δ⁻¹ K|v[n−1]+a|)ε _(n)+δ⁻¹ Kb _(e)[n],   (23)

where ε _(n) and b _(e)[n] are the expected values of ε_(n) andb_(e)[n], respectively, conditioned to the sequence v[n−1].

When δ≠1, the self-dithering property of the ΔΣ FDC is not perfect, soe_(qr)[n] can be correlated with sgn(v[n−1]+a). Furthermore, it followsfrom FIG. 1 that:

$\begin{matrix}{{p\lbrack n\rbrack} = {{- {e_{q}\lbrack n\rbrack}} + {e_{q}\left\lbrack {n - 1} \right\rbrack} + {\sum\limits_{i = 0}^{n}{y\lbrack i\rbrack}} + \alpha}} & (24)\end{matrix}$

so FIG. 5B and v[n−1]=y[n−2] imply that the termΨ_(PLL)[n]=θ_(PLL)(τ_(n)) θ_(PLL)(τ_(n−1)) in e_(pLL)[n], which dependson a low-pass filtered version of p[n], can also be correlated withsgn(v[n−1]+a). As b_(e)[n] depends on both e_(qr)[n] and e_(PLL)[n], itfollows from these observations that b _(e)[n] in (23) is not zero, sob_(e)[n] biases the LMS loop (see FIGS. 6 and 7) and causes g_(n) toconverge to a value that is slightly different than δ. However, numeroussimulations suggest that the magnitude of this bias is sufficientlysmall that b _(e)[n] can be neglected in the remainder of the analysis.Hence, (23) reduces to

ε _(n+1)=(1−δ⁻¹ K|v[n−1]+a|)ε _(n).   (25)

The recursive application of (25) to itself yields

$\begin{matrix}{{{\overset{¯}{ɛ}}_{n + 1} = {\prod\limits_{i = 0}^{n}{\left( {1 - {\delta^{- 1}K{{{v\left\lbrack {i - 1} \right\rbrack} + \alpha}}}} \right){\overset{¯}{ɛ}}_{0}}}},} & (26)\end{matrix}$

which implies that, on average, ε_(n+1) tends to zero provided K ischosen such that

$\begin{matrix}{{\lim\limits_{n\rightarrow\infty}{\prod\limits_{i = 0}^{n}\left( {1 - {\delta^{- 1}K{{{v\left\lbrack {i - 1} \right\rbrack} + \alpha}}}} \right)}} = 0.} & (27)\end{matrix}$

As |v[n−1]+a| is bounded and is regularly non-zero, (27) is easy tosatisfy in practice.

FIG. 8A shows a charge pump (CP)-based ΔΣ FDC 800. It consists of aphase-frequency detector (PFD) 802 with output u(t), a charge pump (CP)804 that charges and discharges the capacitor C, an analog-to-digitalconverter (ADC) 806 driven by an output of the CP 804, a multi-modulusdivider 808 with output v_(div)(t), and a 2−z⁻¹ digital feedbackcircuitry 810 with output v[n]. It also comprises a One-shot circuit 812that prevents the magnitude of the CP output to grow without bound. ThePFD 802 and divider 808 are identical to those in analog PLLs.

The digital gain correction method of FIG. 6 is also applicable to acharge pump-based ΔΣ FDC. FIG. 8A shows a CP based ΔΣ FDC, and FIG. 8Bthe modified version with the digital gain correction of FIG. 6. Theonly one difference in FIG. 8B compared to FIG. 6 is an extra 1−z⁻¹differentiator. In the CP-based ΔΣ FDC, the CP and subsequentanalog-to-digital converter (ADC) play the same role as the DMRO in theDMRO-based ΔΣ FDC. The DMRO-based ΔΣ FDC already has a 1−z⁻¹differentiator following the DMRO, which is needed as part of thecircuitry that makes it possible to read out the DMRO's phase error, butthis differentiator is not necessary in the CP-based ΔΣ FDC. Theadditional 1−z⁻¹ differentiator in FIG. 8B compensates for the absenceof a 1−z⁻¹ differentiator at the output of the ADC in the CP-based ΔΣFDC architecture.

Delay-Free Asynchronous Phase Sampling.

The invention also provides for delay-free asynchronous phase samplingof the DMRO 204 in FIG. 2B or more generally, any system where the phaseof a ring oscillator (RO) needs to be sampled with a clock signalasynchronous to the RO's frequency. FIG. 9 shows a preferred embodimentdelay-free asynchronous phase sampling method 900 to sample a RO 902.The method uses a digital cycle counter 904 followed by samplingflip-flops 905 and 907 and a digital phase decoder 909. Sampling of thecycle counter's outputs is a variation of the asynchronous samplingscheme presented in J. Daniels, W. Dehaene and M. Steyaert, “All-digitaldifferential VCO-based A/D conversion,” IEEE Int. Symp. Circuits Syst.,pp. 1085-1088, June 2010. We provide a new phase decoder implementationof asynchronous sampling that is insensitive to initial conditions.

The cycle counter includes two counters 906 and 908 (of 4 bits each inthis example). The counter with output c_(pos)(t) is clocked with therising edge of the RO's cell with output d₁(t), whereas the counter withoutput c_(neg)(t) is clocked with the falling edge of d₁(t). On eachrising edge of v_(samp)(t), the counter outputs c_(pos)(t) andc_(neg)(t) are sampled to generate c_(pos)[n] and c_(neg)[n], and the ROoutputs d₁(t), d₂(t), . . . , d₁₂₇(t) are sampled to generate d₁[n],d₂[n], . . . , d₁₂₇[n]. The phase decoder consists of a lookup table(LUT) 910 that quantizes the sampled RO outputs to form a sequence,p_(F)[n], which represents the fractional part of the sampled RO phase,and the overall logic in the phase decoder 909 computes p_(I)[n], whichrepresents the integer part of the sampled RO phase.

The top and bottom counters 906 and 908 in the cycle counter are clockedwhen p_(F)[n]≅0 and p_(F)[n]≅126Δ, respectively, where Δ=1/254 in theexample case shown in FIG. 9. Hence, p_(F)[n] can be used to determinewhich counter output was not changing when the sampling event occurred.As shown in FIG. 9, whenever the RO fractional phase, p_(F)[n], isbetween 63Δ and 189Δ, p_(I)[n] is set to c_(pos)[n]. Ideally, p_(I)[n]should be set to c_(neg)[n] when p_(F)[n] is between 190Δ and 253Δ, andto c_(neg)[n]+1 when p_(F)[n] is between 0 and 62Δ so as to account forthe bottom counter being clocked half an RO cycle after the top counteris clocked. Yet to work correctly this would requirec_(pos)(0)=c_(neg)(0) and the initial RO fractional phase to be suchthat the top counter is clocked before the bottom counter after startup,which are hard to ensure in practice.

These requirements are avoided via the c_(corr)[n] correction logic 912.As both sampled counter outputs are reliable when p_(F)[n] is around 63Δand 190Δ, the c_(corr)[n] logic block 912 in FIG. 9 computes

$\begin{matrix}{{c_{corr}\lbrack n\rbrack} = \left\{ \begin{matrix}{{{c_{pos}\lbrack n\rbrack} - {c_{neg}\lbrack n\rbrack} - 1},} & {{{{if}\mspace{14mu} {p_{F}\lbrack n\rbrack}} \in \left\lbrack {{53\Delta},{73\Delta}} \right\rbrack},} \\{{{c_{pos}\lbrack n\rbrack} - {c_{neg}\lbrack n\rbrack}},} & {{{{if}\mspace{14mu} {p_{F}\lbrack n\rbrack}} \in \left\lbrack {{180\Delta},{200\Delta}} \right\rbrack},} \\{c_{corr}\left\lbrack {n - 1} \right\rbrack} & {{otherwise},}\end{matrix} \right.} & (28)\end{matrix}$

and, as shown in FIG. 9, p_(I)[n] is set to c_(neg)[n]+c_(corr)[n] whenp_(F)[n] is between 190Δ and 253Δ, to c_(neg)[n]+c_(corr)[n]+1 whenp_(F)[n] is between 0 and 62Δ, and to c_(pos)[n] otherwise i.e,

$\begin{matrix}{{p_{I}\lbrack n\rbrack} = \left\{ \begin{matrix}{{{c_{neg}\lbrack n\rbrack} + {c_{corr}\lbrack n\rbrack}},} & {{{{if}\mspace{14mu} {p_{F}\lbrack n\rbrack}} \in \left\lbrack {{190\Delta},{253\Delta}} \right\rbrack},} \\{{{c_{neg}\lbrack n\rbrack} + {c_{corr}\lbrack n\rbrack} + 1},} & {{{{if}\mspace{14mu} {p_{F}\lbrack n\rbrack}} \in \left\lbrack {{0\Delta},{62\Delta}} \right\rbrack},} \\{c_{pos}\lbrack n\rbrack} & {{otherwise}.}\end{matrix} \right.} & (29)\end{matrix}$

The sequences p_(I)[n] and p_(F)[n] are combined at the output of thephase decoder 909 to form the sequence p[n], which represents thesampled RO phase comprising both integer and fractional parts.

All arithmetic operations within the phase decoder 906 and itsc_(corr)[n] logic block 912, are performed with 2^(C)-modulararithmetic, where C is the number of bits of the counters within thecycle counter 904 (e.g., C=4 in the example case shown in FIG. 9).

Incremental Frequency-Switching Controller

FIG. 10A shows a PLL including a DCO. FIG. 10B shows the basic structureof the a DCO.

In FIG. 10A, a reference oscillator 1002 generates an f_(ref)-rateperiodic signal, v_(ref)(t), which is used, along with the PLL's outputv_(PLL)(t), by the phase-error to digital converter (PEDC) 1004 togenerate a quantized measure of the PLL's instantaneous phase error. ThePEDC f_(ref)-rate output, p[n], is further lowpass filtered by thedigital loop filter (DLF) 1006, whose output, d[n], is used to controlthe instantaneous frequency, f_(PLL)(t), of a DCO 1008

In the DCO 1008, the minimum achievable frequency-step is dictated bythe FCE's minimum frequency step size, Δ_(min), which, for manyapplications, is larger than the desired frequency step, Δ. FIG. 10Bshows a generalization of a common solution to this problem. Thef_(ref)-rate D-bit sequence d[n] is split into two digital sequences,d_(I)[n] and d_(F)[n]. d_(I)[n] consists of the I-MSBs of d[n] and willbe referred to as the integer-part of d[n] because it causes the DCOfrequency to change by integer multiples of Δ_(min), whereas d_(F)[n]consists of the F-LSBs of d[n] and will be referred to as thefractional-part of d[n] because it causes the DCO frequency to change infractional-steps of Δ_(min).

To achieve frequency steps that are a fraction of Δ_(min), d_(F)[n] isdigitally re-quantized to an f_(fast)-rate (usually f_(fast)>f_(ref))B-bit sequence, d_(Fq)[n], where d_(Fq)[n] is equal to d_(F)[n] plussome quantization error, usually high-pass shaped. The parameters Amin,F, B, ffast and the digital re-quantizer architecture are chosen suchthat the extra noise resulting from the quantized frequency-tuningprocess does not deteriorate the PLL's phase noise profile.

The way d_(I)[n] and d_(Fq)[n] are combined and translated into DCOfrequency changes depends on the DCO topology. FIG. 11 shows an examplefor the frequency control in an LC-DCO. In the example, the FCE'sminimum frequency-step Δ_(min)=2⁸Δ, where Δ is the desired frequencystep. This requires the split of the two's complement 16-bit sequenced[n] into two 8-bit sequences, d_(I)[n] and d_(F)[n]. The digitalre-quantizer is implemented as a second-order digital ΔΣ modulator(ΔΣM), and d_(Fq)[n] is further thermometer encoded. Each of d_(I)[n]and d_(Fq)[n] control an array of FCEs, where each FCE adds to orsubtracts from the total tank capacitance, depending on its digitalinput, hence, controlling the DCO's frequency.

While in the acquisition-mode, the PLL's negative feedback mechanismtries to set d[n] to the right value such that the DCO runs at thedesired frequency. During this phase, d[n] experiences a transientbehavior determined by the PLL's initial conditions and loop dynamicsand changes in d_(I)[n] are normal. Once lock is acquired, d[n]converges to a constant number whose value sets the PLL to run at thedesired frequency, and the PLL is said to run in the tracking-mode. Inthis mode, d[n] would vary around this constant value in response to thePLL's phase error in addition to other noise terms incurred during thePEDC process. In many applications, the low-noise system-levelrequirements imply that d_(I)[n] remains constant, and only d_(F)[n]would change in response to the noise sources in the PLL. Occasionally,however, d_(I)[n] would change due to the DCO's flicker noise andtemperature induced frequency drifts, but this happens at a much lowerrate than the changes in d_(F)[n].

FIG. 12 shows a preferred IFS controller 1200 in the context ofcontrolling an LC-DCO like that shown in FIGS. 10A and 10B. The DCO'sfrequency is controlled by an array of N equally weighted FCEs whereeach FCE adds to or subtracts from the overall tank capacitance (achange in an FCE's state from 0 to 1 corresponds to an increase in theDCO's running frequency by Δ_(min)). The FCE bank is controlled by thesignals c₁[n] and c₂[n] and their inverted versions. The signals c₁[n]and c₂[n] are generated within the DCO's digital interface, which hasincremental-switching logic (ISL) 1202 and an incremental-switchingfinite-state machine (IS -FSM) 1204.

FIG. 13 is illustrative example describing how the IFS controller 1200operates. In this example, the DCO's digital interface is clocked at arate f_(fast)=f_(PLL)/5, the PLL's frequency f_(PLL)=20f_(ref), d[k] andd[k+1] are 2.25 and 2.5, respectively, and the FCE bank has 20equally-weighted elements, FCE0 to FCE19, where d[n]=0 corresponds tothe first 10 elements having a “1” state. For the DCO to have the right“average” frequency, in this example, the 12^(th) FCE must have a “1”state once and twice over the k^(th) and (k+1)^(th) reference periods,respectively. In the IFS control scheme, c₁[n] and c₂[n] control thewhole FCE bank in accordance to the “move” signal, m[n], which dictatesthe number of FCEs having a “1” state to increment (go up) by one,decrement (go dn) by one, or to not change (noc). The ISL output thesignal m[n] that takes on a value of −1, 0, or 1, corresponding to adecrease in the DCO's frequency by Δ_(min) (dn), no frequency change atall (noc), or an increase by Δ_(min) (up), respectively. The IS-FSMgenerates c₁[n] and c₂[n] (and their inverted versions), each taking ona value of 0, or 1, based on m[n], c₁[n−1] and c₂[n−1].

The DCO 1008 (FIG. 10A) can be implemented as an analog LC-oscillatorwhose frequency is controlled by digitally changing the state of the FCEbank's unit cells. The oscillator consists of an inductor, a fixedcapacitance, an NMOS cross-coupled transistor pair, and a tail currentsource. The IFS scheme, however, can be applied to any DCO topologywhose frequency can be tuned by discrete switching of an FCE where achange in the FCE's binary-state results in either an increase or adecrease in the oscillator's frequency.

FIG. 14A shows the FCE bank which consists of N nominally identical unitcells. In the shown version, each unit cell is controlled by eitherc₁[n] or c₂[n], in an alternating fashion, through an intra-network ofswitches. In the fully differential version, each unit is differentiallycontrolled by c_(i)[n], where i=1 or 2, and its inversion. The FCE bankuses a modified FCE unit which will be referred to as latched-FCE(LFCE), and in the presented scheme there are two types of LFCEs, LFCE-0and LFCE-1. FIG. 14B shows the LFCEs' details. An LFCE is a regular FCEwhose control voltage is latched by a pair of cross-coupled tri-stateinverters to keep the FCE's control logic value when the FCE cell isdisconnected from its respective control signal. Both LFCE types areidentical except for the polarity of c_(i)[n] that controls the FCE'sstate. In LFCE-0 (LFCE-1), a control state 0 (1) results in an increasein the DCO's frequency. The FCE bank has the LFCE-x units arranged suchthat x follows the pattern { . . . , 1, 0, 0, 1, 1, 0, 0, 1, . . . } forreasons that will be explained shortly. In this implementation, each FCEhas a topology to achieve small frequency steps, but any otherswitched-capacitor topology could have been used. The FCE bank frequencyincreases monotonically as the number of FCEs with a “1” state increases(as in thermometer coded schemes) and is initialized at mid-frequency asshown in FIG. 5A. A global reset signal (rst) is used to initialize theFCE bank to its hard-coded initial conditions (ic). In a variation, theDCO has multiple banks of FCEs, each of which is controlled by its owntwo-wire interface.

The switches' network guarantees that only two LFCEs are active overevery fast clock period, i.e., only two LFCEs are accessible by thecontrol signals, one through c₁[n] and the other through c₂[n]. Theswitches arrangement that achieves such functionality is shown in FIG.14A. Since over each f_(fast) clock period we have access to two FCEs,one at state “0” and the other at state “1”, the IFS controller 1200 canbe easily implemented. For the setting shown in FIG. 14A, the DCO' sfrequency can move up, dn, or noc by setting the logic states of c₁[n]and c₂[n] to (1, 1), (0, 0), or (c₁[n−1]=0, c_(2[n−)1]=1), respectively.The LFCE-x pattern, x={ . . . , 1, 0, 0, 1, 1, 0, 0, 1, . . . }, isintentionally chosen to avoid short-circuiting two different LFCE statesduring control signals' transitions. In this implementation, theswitches in FIG. 14A are implemented using CMOS-switches.

Without loss of generality, the digital blocks' bus widths and signalprocessing details are presented within the context of an implementationexample. FIG. 15A shows details of a preferred ISL implementation andFIG. 15B a state diagram for operation. For a desired minimum frequencystep=2 ⁻⁸Δ_(min), the 16-bit two's complement sequence d[n] is splitinto its integer and fractional parts, d_(I)[n] and d_(F)[n],respectively, each of which is an 8-bit f_(ref)-rate sequence. Asuccessive re-quantizer which can be configured to have first- orsecond-order high-pass shaped quantization error is used to generate thef_(fast)-rate sequence d_(Fq)[n] which can take on values of 0 or 1.d_(Fq)[n] is added to anffast-rate up-sampled and zero-order heldversion of d_(I)[n] generating the sequence h[n] which represents thenumber of FCEs that should have a “1” state over a given fast clockperiod. To generate m[n], h[n] is compared to the current number of FCEswith “1” state, t[n−1] (a delayed and accumulated version of m[n]), todetermine how many increments/decrements are needed. As explained above,usually the increments/decrements are limited to unity. In theoccasional case where increments/decrements by more than one are needed,the difference between h[n] and t[n−1] is clipped to ±1, since the FCEbank topology can only handle increments/decrements by one, and thedifference is added to the next cycle as if the changes in h[n] where“serialized”. Since this scenario might only take place during the PLL'sacquisition mode or at a very slow rate when d_(I)[n] crosses aninteger-boundary, the serialization action has no significant impact onthe DCO's phase noise profile.

Once m[n] is ready, the FCE bank control signals c₁[n] and c₂[n] aregenerated by the IS-FSM. The IS-FSM finite-state transition diagram isshown in FIG. 15B where c₁[n], for i=and 2, and their inverted versionsare generated based on m[n](upldnInoc), c₁[n−1] and c₂[n−1]. Notice thateither c₁[n] or c₂[n] changes its state at any given transition but notboth, reducing the number of toggling digital lines controlling the FCEarray to its minimum. This happens independent of the DCO's input codeword and of any timing mismatches, alleviating a fundamental problem inprior DCO frequency switching schemes. The present controller uses apair of differential digital control signals to control the whole FCEbank, where at most one of the control signals changes its state at atime. This property is maintained across all DCO input values and isimmune to any inevitable timing mismatches. The controller adds minimalhardware to existing FCE topologies which makes it suitable forlow-power and small-area applications.

While specific embodiments of the present invention have been shown anddescribed, it should be understood that other modifications,substitutions and alternatives are apparent to one of ordinary skill inthe art. Such modifications, substitutions and alternatives can be madewithout departing from the spirit and scope of the invention, whichshould be determined from the appended claims.

Various features of the invention are set forth in the appended claims.

1. A delta-sigma frequency-to-digital converter, comprising: aphase-frequency detector that receives a periodic reference signal; adual-mode ring oscillator driven by an output of the phase-frequencydetector; a ring phase calculator that samples outputs of the dual-modering oscillator to calculate phase of the dual-mode ring oscillator;within the ring phase calculator, digital feedback to an accumulator inthe ring phase calculator that provides the converter output; andfeedback of a delayed version of the converter output through a dividerto the phase-frequency detector.
 2. The converter of claim 1, furthercomprising an adder to subtract a constant from an input of theaccumulator, the constant being selected to force average frequency ofthe dual-mode ring oscillator to its reference frequency.
 3. Theconverter of claim 1, wherein the dual-mode ring oscillator operates ina fixed frequency range with fixed values of the high and lowfrequencies without analog gain correction from feedback in thedual-mode ring oscillator.
 4. The converter of claim 1, furthercomprising digital background calibration in the ring phase calculator.5. The converter of claim 4, wherein the digital background calibrationcomprises a feedback loop driven by an intermediate node of the ringphase calculator that compensates for ΔΣ FDC forward path gain errorcaused by non-ideal DMRO frequencies
 6. The converter of claim 1,wherein the ring phase calculator comprises: a cycle counter and phasedecoder that samples the outputs of the dual-mode ring oscillator; adifferentiator that generates phase change of the dual-mode ringoscillator over a period of the periodic reference signal; a first adderadding a constant to the output of the differentiator; a multiplier thatmultiples an output of the first adder; a second adder adding acorrection sequence to an output of the multiplier and the digitalfeedback; and an accumulator that receives output of the second adder.7. The converter of claim 1, in a phase-locked loop (PLL), wherein anoutput span of the phase-frequency detector is smaller than twice theperiod of PLL output.
 8. The converter of claim 1, wherein the dividerloads its modulus near beginning of a current count.
 9. The converter ofclaim 1, comprising digital background calibration in the ring phasecalculator that allows the dual-mode ring oscillator to operate withoutanalog correction of its frequency.
 10. The converter of claim 9,wherein the digital background calibration ramps g_(n) (gain calibrationoutput) up or down until an input to the accumulator reaches zero-meannoise.
 11. The converter of claim 9, wherein the digital backgroundcalibration comprises a signed least-mean square (LMS)-like loop withgain K and output g_(n), which digitally compensates for forward pathgain error caused by δ≠1 (forward gain in the absence of gaincorrection).
 12. The converter of claim 1, wherein the ring phasecalculator comprises a ring oscillator delay-free asynchronous phasesampler sampling outputs of an RO comprising: a cycle counter with twocounters clocked by the rising and falling edges, respectively, of theoutput of the RO; a phase decoder to process the outputs of the RO andto select a sampled counter output that was not changing when thesampling event occurred; correction logic to compensate for arbitraryinitial conditions of the RO and counters within the cycle counter. 13.The sampler of claim 12, wherein the phase decoder comprises: a look-uptable (LUT) to form a sequence that represents a sampled fractionalphase of the RO; correction logic to compute a difference betweensampled outputs of the cycle counter; and logic to determine sampled ROinteger phase from an output of the correction logic and the sampledoutputs of the cycle counter.
 14. A frequency-to-digital converter,comprising: a phase-frequency detector that receives a periodicreference signal; a charge pump that charges and discharges a capacitor;a one-shot circuit that prevents the magnitude of the charge pump outputto grow without bound; an analog-to-digital converter driven by anoutput of the charge pump; a multi-modulus divider providing feedback tothe phase-frequency detector; and digital background calibrationprovided by multiplier at the output of the analog-to-digital converterto correct for deviations of charge pump currents and capacitance ofcapacitor from their ideal values.
 15. A ring oscillator delay-freeasynchronous phase sampler sampling outputs of a ring oscillator (RO)comprising: a cycle counter with two counters clocked by the rising andfalling edges, respectively, of the output of the RO; a phase decoder toprocess the outputs of the RO and to select a sampled counter outputthat was not changing when the sampling event occurred; correction logicto compensate for arbitrary initial conditions of the RO and counterswithin the cycle counter.
 16. The sampler of claim 15, wherein the phasedecoder comprises: a look-up table (LUT) to form a sequence thatrepresents a sampled fractional phase of the RO; correction logic tocompute a difference between sampled outputs of the cycle counter; andlogic to determine sampled RO integer phase from an output of thecorrection logic and the sampled outputs of the cycle counter.
 17. Adigitally-controlled oscillator (DCO) control method that causes the DCOfrequency to increase or decrease by changing the state of one itsfrequency control elements (FCEs) at a time, comprising a bank of FCEsto control the DCO frequency, the FCE bank having an array oflatched-FCEs (LFCEs); a digital interface that accepts an input codeword and outputs two control signals and their inverted versions tocontrol the FCEs' bank; the array of LFCEs being connected to thecontrol signals through an intra-network of switches, with each topswitch being controlled by the state of the LFCE to its right (or aninverted version of it) and each bottom switch being controlled by thestate of the LFCE to its left (or an inverted version of it); a DCOdigital interface that includes an incremental switching logic (ISL) andan incremental-switching finite-state-machine (IS-FSM); wherein the ISLsplits the input codeword into its integer and fractional parts,digitally re-quantizes the fractional part and adds it to the integerpart of the input codeword.
 18. The DCO control method of claim 17, anoutput of the ISL operation is passed through control logic including aclipper, an accumulator, a carry-generator and an adder.
 19. The DCOcontrol method of claim 18, wherein the control logic outputs changes inits input and the carry is added to the next sample, to serialize achange in the control logic input.
 20. The DCO control method of claim19, wherein the changes in its input are limited to ±1 and an output ofthe ISL is a signal that takes on values from {−1, 0, 1} and is passedto the IS-FSM, wherein the IS-FSM generates two control signals andtheir inverted versions that control the array of LFCEs.